Exemplary embodiments relate to a semiconductor device and methods of manufacturing the same and, more particularly, to a non-volatile memory device having a three-dimensional (3-D) structure and methods of manufacturing the same.
A non-volatile memory device is a memory device that retains stored data even after a power supply is cut off. As the integration degree of two dimensional (2-D) memory devices with one layer of memories formed on a silicon substrate is reaching physical limits, three dimensional non-volatile memory devices having memory cells that are stacked vertically from a silicon substrate are being developed.
An example of a known three dimensional non-volatile memory device and features thereof are described in detail below.
FIG. 1 is a cross-sectional view illustrating the structure of a known charge trap-type non-volatile memory device having a three dimensional structure and a method of manufacturing the same.
As shown in FIG. 1, a plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 are alternately formed over a substrate 10 in which a source region (not shown) is formed. Trenches through which a surface of the substrate 10 is exposed are formed by etching the interlayer dielectric layers 11 and the conductive layers 12. A gate insulating layer 13 is formed on the inner walls of the trenches. The trenches are filled with a layer for a channel, thereby forming channels CH. Accordingly, a lower selection transistor LST is formed.
Next, a plurality of interlayer dielectric layers 14 and a plurality of conductive layers 15 are alternately formed over the resulting structure in which the lower selection transistor LST is formed. Here, the number of stacked interlayer dielectric layers 14 and the number of stacked conductive layers 15 are determined by the number of memory cells to be stacked.
Next, trenches through which the channels CH of the lower selection transistor LST are exposed are formed by etching the interlayer dielectric layers 14 and the conductive layers 15. Next, a charge blocking layer, a charge trap layer, and a tunnel insulating layer 16 are sequentially formed on the inner walls of the trenches. The trenches are filled with a layer for a channel, thereby forming channels CH. Here, the charge trap layer is used as a data storage space for storing or erasing data by trapping or discharging charges. According to an example, the charge trap layer is formed of a nitride layer. Accordingly, a plurality of memory cells MC is formed.
Next, a plurality of interlayer dielectric layers 17 and a plurality of conductive layers 18 are alternately formed over the plurality of memory cells MC. Trenches through which the channels CH of the memory cells MC are exposed are formed by etching the interlayer dielectric layers 17 and the conductive layers 18. Next, a gate insulating layer 19 is formed on the inner walls of the trenches. The trenches are filled with a layer for a channel, thereby forming channels CH. Accordingly, an upper selection transistor UST is formed.
Here, the plurality of memory cells MC is coupled in series between the lower selection transistor LST and the upper selection transistor UST, thus forming one string ST. Each of the channels CH is coupled to a bit line BL.
According to the above-described steps, the three dimensional charge trap-type non-volatile memory device including the charge trap layer for enabling each of the memory cells MC to trap charges may be formed. However, the charge trap-type non-volatile memory device has characteristics inferior to a floating gate-type non-volatile memory device for storing data by injecting charges into or discharging charges from the floating gate.
For example, a charge trap-type non-volatile memory device has slower program/erase operation speeds than a floating gate-type non-volatile memory device and also has data retention characteristics inferior to the floating gate-type non-volatile memory device. Here, the data retention characteristic may be degraded because the charge trap layers of the plurality of memory cells stacked along the channels are interconnected to each other.